About the Role
We are looking for a motivated Physical Design (PD) Engineer to join our semiconductor engineering team. The candidate will contribute to physical implementation across IP/block, subsystem, and full-chip/SoC levels, taking designs from synthesized netlists through physical sign-off. The role involves physical implementation, optimization, timing closure, integration of macros and IPs, and analysis of power, performance, area, and physical constraints.
What You'll Do
- Work across floorplanning, power planning, placement, clock tree synthesis, routing, optimization, and physical sign-off.
- Implement and optimize blocks, IPs, subsystems, and full-chip/SoC designs.
- Integrate standard cells, memories, hard macros, analog IPs, IOs, and other physical blocks.
- Analyze and optimize setup/hold timing, congestion, power, area, and signal integrity.
- Perform multi-corner/multi-mode analysis and support timing closure.
- Support clock and power distribution, physical constraints, and hierarchical implementation.
- Perform ECO implementation and resolve physical and timing issues.
- Analyze implementation and sign-off reports and drive design closure.
- Collaborate with RTL, STA, DFT, PV, package, and sign-off teams.
Required Skills
- Good understanding of the ASIC physical design flow.
- Knowledge of floorplanning, power planning, placement, CTS, routing, and timing closure.
- Understanding of setup/hold, clock skew, constraints, parasitics, and PPA.
- Understanding of block-level and top-level physical integration.
- Good analytical and debugging skills.
Good to Have
- Advanced-node implementation and hierarchical SoC implementation.
- Low-power/UPF, IR drop, EM, signal integrity, and physical sign-off.
- Integration of HBM, high-speed IO, memories, analog macros, and chiplet-related physical structures.
- TCL, Python, Perl, or shell scripting.
Educational Qualification
B.E./B.Tech/M.E./M.Tech in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, VLSI, Microelectronics, or a related field.
What We Look For
- Strong technical fundamentals and a practical engineering mindset.
- Ability to understand specifications and solve complex technical problems.
- Effective debugging, analysis, and communication skills.
- Ability to work independently and collaboratively across engineering teams.
- Curiosity and willingness to learn new semiconductor technologies and methodologies.
What You Will Work On
- IP/Block Implementation
- Subsystem Implementation
- Full-Chip/SoC
- Floorplanning
- Placement
- CTS
- Routing
- Timing Closure
- PPA Optimization
- Advanced Nodes
- HBM
- Chiplets
Closing Statement
Implement high-performance, power-efficient and area-conscious semiconductor designs through physical closure and sign-off.