About the Role
We are looking for a motivated DFT Engineer to join our semiconductor engineering team. The candidate will contribute to DFT activities across IP/block, subsystem, and SoC levels, from test architecture and insertion through pattern generation, verification, coverage analysis, and sign-off.
What You'll Do
- Understand DFT requirements and contribute to test architecture and methodology development.
- Implement and integrate scan, test compression, and other DFT structures at block and SoC levels.
- Develop and analyze ATPG patterns, fault models, and test coverage.
- Support MBIST, LBIST, boundary scan, and IJTAG methodologies where applicable.
- Perform DFT insertion, verification, simulation, timing-aware pattern validation, and debug.
- Integrate DFT logic and test access structures across hierarchical designs.
- Analyze coverage and test-quality reports and resolve DFT implementation issues.
- Support DFT sign-off, diagnosis, and silicon-test readiness.
- Collaborate with RTL, physical design, verification, product, manufacturing, and silicon teams.
Required Skills
- Good understanding of Digital Design and DFT fundamentals.
- Knowledge of scan chains, ATPG, fault models, compression, and test coverage.
- Understanding of DFT insertion, verification, and hierarchical test concepts.
- Good analytical and debugging skills.
Good to Have
- MBIST, LBIST, boundary scan, IJTAG, memory repair, and diagnosis.
- IEEE 1149.1, IEEE 1500, or IEEE 1687.
- DFT-aware timing, physical implementation, and low-power test concepts.
- TCL, Python, Perl, or shell scripting.
Educational Qualification
B.E./B.Tech/M.E./M.Tech in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, VLSI, Microelectronics, or a related field.
What We Look For
- Strong technical fundamentals and a practical engineering mindset.
- Ability to understand specifications and solve complex technical problems.
- Effective debugging, analysis, and communication skills.
- Ability to work independently and collaboratively across engineering teams.
- Curiosity and willingness to learn new semiconductor technologies and methodologies.
What You Will Work On
- Block-Level DFT
- SoC DFT Integration
- Scan
- ATPG
- Test Compression
- MBIST
- LBIST
- Boundary Scan
- IJTAG
- Memory Test
- Fault Coverage
- Diagnosis
Closing Statement
Develop test solutions that improve semiconductor testability, manufacturing coverage, diagnosis, and silicon readiness.