The role
Join our DFT team to architect and implement test strategies that maximize fault coverage while minimizing test cost across our SoC portfolio.
What you'll do
- Implement scan insertion, ATPG, MBIST, and boundary scan.
- Develop DFT architecture and test compression strategies.
- Generate and validate test patterns; analyze fault coverage.
- Support wafer sort and final test pattern bring-up.
- Collaborate with PD teams on DFT-aware physical implementation.
Required qualifications
- Bachelor’s or Master’s in ECE or related field.
- 4+ years of DFT implementation experience.
- Hands-on with ATPG tools and scan methodologies.
- Understanding of fault models and coverage metrics.