The role
We are looking for a Senior RTL Design Engineer to own microarchitecture and RTL implementation for complex SoC subsystems. You will translate architectural specifications into synthesizable, high-quality RTL and drive design closure alongside verification and physical design teams.
What you'll do
- Develop microarchitecture specifications and synthesizable RTL in SystemVerilog.
- Own block-level design from specification through synthesis and timing closure.
- Implement low-power design techniques (clock gating, power domains, UPF).
- Collaborate with verification teams on testbench planning and coverage closure.
- Perform lint, CDC, and RDC analysis to ensure clean, robust designs.
Required qualifications
- Bachelor’s or Master’s in Electrical/Electronics Engineering or related field.
- 6+ years of hands-on RTL design experience on production silicon.
- Strong proficiency in SystemVerilog and digital design fundamentals.
- Experience with synthesis, timing constraints (SDC), and STA concepts.